An ideal clock switching circuit switches between a set of clock sources without generating glitches. Inputs to clock switching circuit include two asynchronous clocks and a signal which selects one of the clock sources. Output of the clock switching circuit is one of the two asynchronous clock sources depending on the polarity of the signal that selects one of the clock sources. During and after power up (when RESET is released) of the clock switching circuit, glitches can occur at the output of the clock switching circuit. Say CLK 1 and CLK 2 are the two asynchronous signals and CLK 1 is the default clock signal. CLK2 may or may not be active during the power up. If CLK 2 is inactive during power up, then the flip flop that drives an enable of CLK 2 is not known. If this comes up as logic high and CLK 2 is also at logic high, then the output of the clock switching circuit will always be logic high. This issue can be solved by using asynchronous reset to the CLK 2 domain flip flops. Since reset is used asynchronously in the CLK2 domain, when reset is released, a recovery or removal violation can occur on the flip flop which drives the enable of CLK2-AND gate. If the flip flop is settled to ‘1’ then there can be glitch on OR gate output since both clock to OR gate are enabled for 1 or 2 cycles.
Once a clock source has been selected, during the course of operation the selected clock source can be missing or can become faulty. In certain applications, which needs to be fault tolerant, there will be circuitry which can monitor the clocks and indicate the faulty condition. Upon the detection of clock fault, this needs to be rectified by switching to alternate clock source. This can cause problems as the synchronizers of the selected clock source cannot change state due to absence of a clock signal. As a result, the clock switching circuit will never switch to alternate clock source. Basically a deadlock occurs in the circuit.